1. Field of the Invention
This invention relates to a clock signal distributing circuit device and a method for adjusting the phase of a clock signal in digital electronic apparatus, in particular, a large-sized, high-speed computer and so forth.
2. Description of the Prior Art
Recently the operating speed of digital electronic apparatus has been raised higher and higher; nowadays, the cycle of a clock signal is required to be shorter than 10 nanoseconds and its pulse width is also required to be in the range of 1 to 2 nanoseconds. As a consequence, the phase difference between clock signals distributed to respective circuits must be adjusted with an accuracy to less than 1 nanosecond.
Conventional clock signal distributing circuit systems are merely to increase the number of fanouts of an input clock signal and to distribute them. That is, a clock pulse waveform (cycle and pulse width) required in each load circuit is produced by a clock source and divided by a distributing circuit into a plurality of signals, which are each applied directly to a circuit used as a load, for example, a flip-flop, a latch circuit or the like. Since the distributing circuit is formed by ordinary logic gate elements, a waveform shaping effect is produced, but neither the pulse width nor the cycle of the clock signal is changed. In the case of a clock signal of small pulse width and cycle being required, however, if such a waveform is produced by the clock source itself, the waveform becomes dull in the transmission line or in the distributing circuit, or the pulse width undergoes an unwanted change due to a difference between delays in the rise and fall of the signal, resulting in a difficulty in an accurate clock signal supply to all loads.
Further, in order to make the clock signals at the input terminals of all the load circuits in-phase with one another, it is necessary that the transmission lines from the clock source to the load circuits have the same signal delay time. With a conventional method, signals at two load terminals are connected to a two channel oscilloscope via cables of the same length and an adjustment is made so that their waveforms become in-phase with each other on the display surface of the oscilloscope. In the case of the cycle of the clock signal being on the order of nanoseconds, however, a slight difference in the cable length or the accuracy of the phase adjustment in the oscilloscope present a problem to make sufficient phase adjustment difficult.